1. Field of the Invention.
The present invention relates to growth of semiconductor materials and devices, and, more particularly, to heteroepitaxial growth such as gallium arsenide on silicon and devices in such heterostructures.
2. Description of the Related Art.
Many researchers have investigated growth of semiconductor-device quality gallium arsenide (GaAs) on silicon wafers and fabrication of active devices in the GaAs. Such devices would combine the higher mobility of carriers in GaAs with the greater mechanical strength and thermal conductivity of a silicon substrate. For example, R. Fischer et al, GaAs/AlGaAs Heterojunction Bipolar Transistors on Si Substrates, 1985 IEDM Tech. Digest 332, report GaAs/AlGaAs heterojunction bipolar transistors grown on silicon substrates and having current gains of .beta.=13 for a 0.2 .mu.m thick base. Similarly, G. Turner et al, Picosecond Photodetector Fabricated in GaAs Layers Grown on Silicon and Silicon On Sapphire Substrates, 1985 IEDM Tech. Digest 468, report response times of 60 picoseconds for photoconductive detectors fabricated in GaAs on silicon. These articles also note that majority carrier devices such as MESFETs fabricated in GaAs on silicon have performance approaching that of homoepitaxial devices; and this has encouraged efforts to integrate GaAs/AlGaAs optoelectronic and high-frequency devices and silicon devices on the same wafer to utilize hi,h-data-rate optical interconnections to reduce the number of wire interconnections. Selective recrystallization of amorphous GaAs can use the high resistivity of noncrystalline GaAs; see, for example, A. Christou et al, Formation of (100) GaAs on (100) Silicon by Laser Recrystallization, 48 Appl. Phys. Lett. 1516 (1986).
One of the key limitations in the implementation of device structures based on heteroepitaxial GaAs on silicon has been the 4.1% difference in lattice parameters between the two materials. This lattice mismatch leads to the formation of a network of misfit dislocations at the heterointerface; under typical epitaxial growth conditions, a significant fraction of these misfit defects thread away from the interface and into the GaAs regions where devices are subsequently fabricated. It is the presence of these threading dislocations (which can serve as recombination and scattering centers) that has seriously limited the implementation of GaAs on silicon technology.
A number of schemes have been reported for either annihiliating or retarding the propagation of threading dislocations in lattice mismatched semiconductors such as GaAs on silicon. Notably among these is post-growth thermal annealing for defect reduction; see J. W. Lee et al, 50 Appl. Phys. Left. 31 (1987), Choi et al, 50 Appl. Phys. Lett. 992 (1987), and N. Chand et al, 49 Appl. Phys. Lett. 815 (1986). Post-growth annealing by itself has been shown to be effective at reducing the global defect in GaAs layers on silicon substrates; however, there is insufficient data at this time to determine its effectivenes at lowering the density of device degrading threading dislocations. Similarly, Fan et al., U.S. Pat. No. 4,632,712, interrupts the GaAs growth to trap threading dislocations. Alternatively, a number of workers have studied the use of either compositional or thermally cycled superlattices during the growth process for dislocation control; see J. W. Lee, Proc. 1986 Int'l. Symp. on GaAs and Related Compounds 111 (1987), T. Soga et al, 26 Japan. J. Appl. Phys. L536 (1987), R. D. Dupuis et al, 50 Appl. Phys. Left. 407 (1987). It appears from this literature that the primary effect of an intermediary superlattice is to deflect the threading dislocations by the imposition of a strain field (either by thermal effects in the case of the thermally cycled layer or by lattice dilations in the case of chemical superlattices) in such a way that they tend to propagate parallel instead of obliquely to the heterointerface. See Szilagyi et al, 4 J. Vac. Sci. Tech. A 2200 (1986).
However, the known methods still have unacceptably high threading dislocation densities for GaAs epitaxially grown on silicon.
Various researchers have investigated the loss of gallium and aluminum during MBE growth and high temperature treatment of GaAs and Al.sub.x Ga.sub.1-x as; see T. Kojima et al, Layer-by-layer Sublimation Observed by Reflection High-energy Electron Diffraction Intensity Oscillation in a Molecular Beam Epitaxy System, 47 Appl. Phys. Lett. 286 (1985), J. Van Hove et al, Mass-action Control of AlGaAs and GaAs growth in Molecular Beam Epitaxy, 47 Appl. Phys. Lett. 726 (1985), M. Kawabe et al, Preferential Desorption of Ga from Al.sub.x Ga.sub.1-x As Grown by Molecular Beam Epitaxy, 23 Jpn. J. Appl. Phys. L351 (1984), H. Tanaka et al, Single-Longitudinal-Mode Selfaligned (AlGa)As Double-Heterostructure Lasers Fabricated by Molecular Beam Epitaxy, 24 Jpn. J. Appl. Phys. L89 (1985), and R. Heckingbottom, Thermodynamic Aspects of Molecular Beam Epitaxy: High Temperature Growth in the GaAs/Ga.sub.1-x Al.sub.x As System, 3 J. Vac. Sci. Tech. B 572 (1985). The research shows that gallium is lost at a much greater rate than aluminum and Al.sub.x Ga.sub.1-x As actually forms a surface layer of AlAs which retards further loss of gallium.
In emitter-up HBT technology the use of MOCVD to deposit an overgrowth emitter onto a zinc implanted base was recently demonstrated; see J. W. Tully, "A Fully Planar Heterojunction Bipolar Transistor," 7 IEEE Elec. Dev. Lett., 203 (1986) and J. W. Trully, W. Hant, and B. B. O'Brien, "Heterojunction Bipolar Transistors with Ion-Implanted Bases,"7 IEEE Elec. Dev. Lett., 615 (1986) After such an implantation the implanted dopant must be activated and the implant damage must be removed while the surface perfection is maintained since the surface will be the active base/emitter interface. However, known methods have the problem of arsenic loss during the anneal or stress induced by an anneal cap.